MEMS Digital Qualification - Predicting Yield During Initial Design

Overview 

In MEMS and semiconductor design, 20% of the upstream design decisions affect 80% of the downstream foundry processing, packaging, assembly, and system-level performance and yield. Device designers are seldom able to consider the implications of their design decisions on system-level robustness because the tools and workflows to analyze design impacts on device and system yield did not exist. Until now.

In this webinar, we will demonstrate a new fully integrated workflow that begins at the design capture and parametric layout stage of a new device design, brings in process simulation to emulate MEMS/Semi processes steps and create fab-accurate 3D models of devices, and uses cloud simulation to simulate distributions of die, wafer, package, system, and environmental performance outcomes.  We will compare results with measured data supplied by SilTerra, a leader in monolithic CMOS/MEMS foundry services, with test data collected using Polytec test and measurement systems.

At the end of…