Learn how Mentor’s Tanner MEMS solutions, SoftMEMS, OnScale, and statistical analysis tools work together to predict actual device performance and yield of a MEMS device manufactured by SilTerra.
In MEMS and semiconductor design, 20% of the upstream design decisions affect 80% of the downstream foundry processing, packaging, assembly, and system-level performance and yield. Device designers are seldom able to consider the implications of their design decisions on system-level robustness because the tools and workflows to analyze design impacts on device and system yield did not exist. Until now.
In this webinar, we will demonstrate a new fully integrated workflow that begins at the design capture and layout stage of a new device design, brings in process simulation to emulate MEMS/Semi processes steps and create fab-accurate 3D models of devices, and uses cloud simulation to simulate distributions of die, wafer, package, system, and environmental performance outcomes. We will compare results with measured data supplied by SilTerra.
At the end of this webinar, engineers will be empowered to reduce risk, cost, and time-to-market for new MEMS and semiconductor R&D by leveraging MEMS layout to 3D model automation, large-scale efficient 3D modelling, massively scalable Cloud simulation, and Digital Prototyping and Qualification.
What You Will Learn
Learn about how Tanner L-Edit MEMS and SoftMEMS to OnScale simulation workflows enable a paradigm shift in “MEMS Digital Qualification”- the ability to determine device and system-level performance and yield during upstream device design stages.
Who Should View
MEMS process engineers
System engineers, mixed-signal IC designers working at integrated MEMS and IC
Test and verification engineers
Researchers in the field of MEMS
恩萊特科技股份有限公司 Enlight Technology Co., Ltd.
Mentor, A Siemens Business Authorized Distributor