Introduction
The adoption of high-density advanced packaging (HDAP) continues to grow for all kinds of end-user applications. 2.5D integrated circuit (IC) designs using interposers (silicon or organic) generally target high-end applications such as military, aerospace, and high-demand computing, while 3D fan-out packaging approaches like the TSMC integrated fan-out (InFO) package focus more on mass consumption consumer applications like cell phones (figure 1). In addition, all major design houses, foundries, and outsourced semiconductor assembly and test (OSAT) companies are investing in the next level—true die stacking using through-silicon vias (TSVs) and hybrid bonding.
Figure 1. HDAP technologies.
Electronic design automation (EDA) support for HDAP verification has grown right along with the use of HDAP designs. Multiple issues related to HDAP verification have been addressed in HDAP verification solutions:
The development of assembly design kits (ADKs) for package designs [1,2]
Concept of and requirements for assembly-level LVS for advanced packaging [3,4]
Post-layout analog simulation and digital static timing analysis (STA) flows for advanced packaging [5]
Options for generating HDAP system-level connectivity while accounting for die, package, and die/package interface parasitics [6]
Verification options to address the challenge of data incompleteness in 3DIC verification methods [7]
In its simplest form, HDAP physical verification consists of two major requirements:
Connectivity: verifying that multiple die are connected correctly though the package/interposer routing
Alignment: verifying that multiple die are aligned as expected on top of the package/interposer
This basic definition of 2.5/3DIC physical verification is generally considered to be well-established, meaning both the end customers and the ecosystem partners (foundries/OSATs and EDA companies) are aware of and understand the essential requirements. In fact, ecosystem collaboration was the driving force behind the development of 3DIC physical verification design kits that were the beginnings of package ADKs. However, as 3DIC technologies advance and design companies build more complicated HDAP designs, physical verification requirements are expanding. These advanced physical verification requirements are taking 3DIC physical verification to the next level. To keep pace, EDA suppliers are expanding the capabilities of their 3DIC verification tools and strategies.
Calibre 3DSTACK physical verification
The Calibre® 3DSTACK tool was the first automated physical verification system developed specifically for 2.5/3DIC and package design [8]. It has been widely adopted across the ecosystem by OSATs, foundries, and design houses alike, and has enabled many die-package designs (including Siemens’ own emulator technologies) to successfully reach market while avoiding costly re-spins. With the Calibre 3DSTACK tool, designers can perform signoff design rule checking (DRC) and LVS verification of complete multi-die systems at any process node without breaking current tool flows or requiring new data formats. As part of the continuous improvement of the efficiency and accuracy of both the tool and the verification process, critical alignment checks have been enhanced, and an innovative precheck mode has been added to enable designers to find and eliminate selected errors before running signoff.
Die/interposer alignment checking
Alignment checking is one of the essential steps performed during 3DIC verification. The Calibre 3DSTACK overlap and centers checks both verify that multiple die are aligned as expected on top of the package/interposer. The overlap check determines whether or not there is sufficient overlap between the pads of the two interacting die, while the centers check analyzes the centers of the pad pairs to check for any misalignment (figure 2). While both checks accurately cover the basic requirements of alignment checking, debugging and fixing the errors that these checks identify can be challenging.
Figure 2. Basic overlap and centers checks.
False errors in interposer to die checking
For 2.5D assemblies or designs with multiple die on top of an interposer, the basic overlap or centers checks only detects/checks one die at a time, which can result in false errors for any interposer pads that are actually covered by other die (figure 3).
Figure 3. False errors from basic overlap check caused by additional die placed on interposer, but not included in check.
The enhanced overlap and centers checks automatically detect all the die interacting with a given interposer, and check the overlaps/centers of the interposer pads against all die pads at once, eliminating these false errors (figure 4).
Figure 4: Adding intelligent functionality eliminates false errors from enhanced overlap and centers checks caused by multiple die.
While the basic and enhanced checks have the same name, their syntax is different. When two interacting levels in an assembly only have one die, the basic check functionality is sufficient. However, when an interposer has multiple die on the same level (i.e., in the same tier), the enhanced checks should be used.
Debugging centers check misalignment errors
Even without false errors, debugging centers check errors can be challenging, especially when the violation is due to a slight misalignment. Designers must manually calculate the bumps’ centers on the two pads and measure the difference to fix the error. To simplify debugging of centers check errors for misalignments, Calibre 3DSTACK provides the enhanced centers check with the ability to generate special markers/hints pointing to the centers of the pads used for the measurement, making the misalignment explicit during debugging.
Figure 5. Markers for centers check misalignment errors help designers debug these errors quickly and accurately.
Centers check for texted bumps
Traditionally, design teams apply the centers check on all bumps/pads of the specified layer of the die. However, designers are usually specifically interested in detecting any misalignments in texted bumps that represent the pins used for connectivity purposes. The basic centers check does not perform this type of filtering, but the enhanced centers check enables designers to apply the centers check only on texted pads (figure 6).
Figure 6. Selective filtering enables designers to apply centers checks to texted pads only.
Data preparation for 3DIC physical verification
One of the challenges that many design teams face in 3DIC verification flows is effectively managing incomplete data and incorrect setups. The issues may vary from missing data in the input, missing alignment checks that cause problems with die-to-die alignment to go undetected, to systemic issues in which a system-level design flaw results in high errors count. Systemic issues include problems like differences in pin names between layout and source, or missing/incorrectly defined text attachment statements in the deck, both of which generate false connectivity check violations requiring otherwise unnecessary debugging iterations.
To minimize these impacts, the Calibre 3DTSTACK tool provides an innovative precheck mode that allows designers to capture any obvious setup/data issues before invoking the Calibre 3DSTACK signoff run. Although the die are already taped out before the 3D stacking stage, this precheck mode helps catch any early systemic system-level/multi-die integration issues before the Calibre 3DSTACK signoff run. The Calibre 3DSTACK precheck mode includes multiple processes for data and setup issue detection.
Source netlist checking
Source netlist checking detects and reports source netlist syntax issues and verifies correct source to layout mapping. Missing or incorrect mapping definitions between layout and source die can lead to flow termination and/or generation of false connectivity checking violations.
Checking for texted pads
In the Calibre 3DSTACK deck, designers define the text association with the layer representing the pins of the die. Each pin is represented by the ports-pads (a geometry on a user-specified layer) that have the same text label attached to them. The precheck mode detects multiple pad-related issues:
Pads with no texts attached
Pads having more than one text attached
Text labels not associated with any pad (not having any overlap with the geometries of the user-specified pin layer)
Left unaddressed, these issues create connectivity check violations in the Calibre 3DSTACK signoff run.
Missing or extra port checking
Missing or extra port checking determines if pins of the die match in both the layout and source netlists, and reports any missing or extra ports in the layout. There are multiple causes for this type of error—incorrect text association statement in the deck, missing pads, pin name typos, etc. Early detection and fixing of these issues drastically reduces debugging time in the signoff run.
Deck coverage
Deck coverage analyses the die stacking (assembly) and automatically detects die-to-die interactions. It then recommends checks per each die or interacting die pair if any die-to-die interactions are missing in the deck. These recommendations ensure the deck provides full coverage of the assembly verification to prevent any violations (alignment or connectivity) from going undetected.
Power and ground short checking for interposer
Power and ground short checking for interposers applies open/short checking on user-specified power and ground nets for interposer die to help designers get to root cause more quickly. Violations of power/ground connectivity checks are usually the most difficult to debug, since the power and ground nets go across all the die in an assembly and cover large areas in the design, making it a real challenge to find the geometry actually causing a short. Addressing all the issues and applying all the recommendations reported by the Calibre 3DSTACK precheck mode helps design teams drastically reduce their debugging time in the signoff run.
Conclusion
As package designs continue to evolve, so do the verification requirements and challenges. Designers working on even the most complex multi-die, multi-chiplet stacked configurations can use the enhanced check capabilities of Calibre 3DSTACK 3DIC verification to quickly and easily verify that the physical die are placed correctly to ensure proper connectivity and electrical behavior. The precheck mode enables design teams to find and correct basic implementation mistakes and systemic errors before invoking the Calibre 3DSTACK signoff run, eliminating unnecessary debugging iterations and speeding up the overall package verification flow. In addition, integration with the Siemens Xpedition Package Designer (XPD) and Xpedition Substrate Integrator (XSI) tools helps speed implementation, while ties to industry-leading parasitic extraction tools enable capture of coupling across die or package interfaces [9,10]. Extending other traditional IC verification tools, such as reliability verification, to recognize and address package issues, empowers design companies to further enhance the market value of their products [11-13]. Going forward, integrations with additional tools, such as floorplan, place and route, reliability verification, and power, thermal, and stress analyses will provide a more fully automated design-to-manufacture paradigm for the HDAP industry.
The trade name OASIS is a registered trademark in the USA of Thomas J. Grebinski, Alamo, California and licensed for use exclusively by SEMI.
References
J. Ferguson, T. Ramadan, “The Future of Package Design Verification: Assembly Design Kits,” Siemens Digital Industries Software. Oct. 2015. https://resources.sw.siemens.com/en-US/white-paper-the-future-of-package-design-verification-assembly-design-kits
K. Rinebold, K. Felton, “Implementing High-Density-Advanced Packaging for OSATs and Foundries,” Siemens Digital Industries Software. May 2017. https://resources.sw.siemens.com/en-US/white-paper-implementing-high-density-advanced-packaging-for-osats-and-foundries
Tarek Ramadan, “Package designers need assembly-level LVS for HDAP verification,” Siemens Digital Industries Software. Dec. 2017. https://resources.sw.siemens.com/en-US/white-paper-package-designers-need-assembly-level-lvs-for-hdap-verification
Tarek Ramadan, “A deep dive into HDAP LVS/LVL verification,” Siemens digital Industries Software. Sept. 2019. https://resources.sw.siemens.com/en-US/white-paper-a-deep-dive-into-hdap-lvs-lvl-verification
Tarek Ramadan, “System-level, post-layout electrical analysis for high-density advanced packaging,” Siemens Digital Industries Software. Sept. 2018. https://resources.sw.siemens.com/en-US/white-paper-system-level-post-layout-electrical-analysis-for-high-density-advanced
Keith Felton, “Using Calibre for Advanced IC Packaging Verification and Signoff,” Siemens Digital Industries Software. Feb. 2021. https://resources.sw.siemens.com/en-US/white-paper-using-calibre-for-advanced-ic-packaging-verification-and-signoff
Tarek Ramadan, “Crossing the Chasm: Bringing SoC and Package Verification Together with 3DSTACK,” Siemens Digital Industries Software. Jan. 2017. https://resources.sw.siemens.com/en-US/white-paper-crossing-the-chasm-bringing-soc-and-package-verification-together-with
“Calibre 3DSTACK,” Siemens Digital Industries Software. 2015. https://resources.sw.siemens.com/en-US/fact-sheet-calibre-3dstack
J. Ferguson, K. Felton, “Implementing Fan-Out Wafer Level Packaging (FOWLP) with the HDAP Flow,” Siemens Digital Industries Software. June 2017. https://resources.sw.siemens.com/en-US/white-paper-implementing-fan-out-wafer-level-packaging-fowlp-with-the-hdap-flow
K. Rinebold, J. Ferguson, K. Felton, “Surviving the three phases of high density advanced packaging design,” Siemens Digital Industries Software. Aug. 2018. https://resources.sw.siemens.com/en-US/white-paper-surviving-the-three-phases-of-high-density-advanced-packaging-design
Dina Medhat, “Automated ESD protection verification for 2.5D and 3D ICs,” Siemens Digital Industries Software. June 2021. https://resources.sw.siemens.com/en-US/white-paper-automated-esd-protection-verification-for-2-5d-and-3d-ics
Dina Medhat, “2.5D/3D IC latch-up prevention: an automated verification strategy,” Siemens Digital Industries Software. July 2021. https://resources.sw.siemens.com/en-US/white-paper-2-5d-3d-ic-latch-up-prevention-an-automated-verification-strategy
John Ferguson, “Is 3D-IC the next big profit driver?,” EE Times. Oct 23, 2018. https://www.eetimes.com/is-3d-ic-the-next-big-profit-driver/#
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