What is 5G and what are its benefits?
The fifth generation of mobile telecommunications technology, or 5G, is the next generation of wireless network technology, promising faster data speeds and more bandwidth than ever before. What does that mean for the average person? Think about cellphones, for one. People don't just use their phones for calling or texting anymore—they surf the web, check in with social media apps, watch movies, listen to music playlists, write blogs, take and edit videos—you name it! And they do all of these things from wherever they are, not tethered to a wired network. All those different types of connections demand different levels of performance from the phone's network connection.
5G is projected to bring a number of benefits to both consumers and businesses alike, including:
Faster data speeds: 5G provides download speeds of up to 1 Gbps, which is ten times faster than current 4G LTE networks. This speed allows businesses to quickly transfer large files, and consumers to download videos and music in a matter of seconds.
Higher bandwidth: 5G can support significantly higher volumes of data traffic than current networks. Higher bandwidth enables businesses to stream video content without any lag or buffering, and allows consumers to use multiple devices at the same time without experiencing any slowdown in speeds.
Lower latency: 5G is expected to provide latency of around 5-10 ms, which is about 25 times faster than the 50ms latency associated with 4G LTE. This improvement allows for more responsive automated services, such as self-driving cars and remote surgery.
Improved reliability: 5G networks can handle a huge increase in traffic with minimal amounts of congestion and downtime, due in part to its flexible network architecture that makes better use of existing cellular and WiFi frequencies. For consumers, this means fewer dropped phone calls, fewer instances where videos freeze or stream slowly, and fewer delays when downloading large files.
How integrated circuits support 5G networks
To provide this improved functionality, 5G integrated circuits (ICs) contain many different operational blocks, including analog-to-digital converters (ADCs), digital-to-analog converters (DACs), phase-locked loops (PLLs), voltage-controlled oscillators (VCOs), low noise amplifiers (LNAs), and power amplifiers (PAs). Innovations in the design of each block type play an important role in ensuring that the 5G chip can handle the high demands of a high frequency network. ADC blocks convert analog signals into a digital signal to allow a 5G chip to communicate at a faster rate than a 4G or 3G network. However, when too many users are on a 5G network, there may not be enough bandwidth for all of them and it can cause spectral crowding. To reduce the risk of this occurring, engineers improved the ADC block by using two stages of sampling devices, one after the other, to double the resolution, which allows more users per cell and increases the system capacity. Some blocks, such as the PLL, which is used in frequency synthesizers, can exhibit high power consumption when dealing with high traffic loads. This power consumption is lowered by using high-efficiency voltage regulators in the 5G chip, which lowers losses across the whole system to improve efficiency. To optimize battery life on smartphones, engineers designed PAs that consume less energy than previous chip generations. To achieve this design goal, they found ways to create more efficient PAs with higher amplifier efficiency, lower operating voltages, and lower supply voltages, without affecting operation speed or transistor performance. Without such aggressive and innovative changes in the design of these components, the 5G chip would be useless, but aggressive design can also be risky if the layout is not thoroughly and accurately analyzed and characterized before tapeout. Careful and comprehensive analysis decreases the chance of unforeseen issues arising during manufacturing that result in inadequate performance or chip failure. For example, to fulfill the promise of 5G while ensuring the IC designs can be successfully manufactured in commercial quantities, designers of 5G chips and networks need accurate, automated parasitic extraction (PEX) and simulation of IC layouts so they can reduce the impact of parasitics by optimizing their chips before manufacturing.
FD-SOI in 5G
In addition to innovations in block design, 5G chips are on the receiving end of a fundamental shift in process technology. In the past decade, traditional bulk silicon-based transistors were replaced with the fin field-effect transistor (finFET), which is an extension of the planar MOSFET transistor structure. The increased surface area and gate length of finFETs enable much higher performance transistors to be fabricated at ever smaller geometries. However, the significant challenges associated with finFET process technologies limit their applicability for applications such as smartphones or tablets. FinFET devices have issues with drain saturation because designers cannot control the thickness of the gate electrodes, resulting in poor switching characteristics when more devices are turned on in parallel. FinFETs also experience power leakage, which adds even more complexity to circuit design and affects power efficiency. To overcome these issues, fully-depleted silicon-on-insulator (FD-SOI) technologies are becoming increasingly popular in applications such as mainstream mobile applications for 5G, where low-power needs are combined with demand for high performance. FD-SOI processes offer many advantages over finFETs that make them more suitable for low-power applications, including lower leakage current and faster switching times resulting from reduced parasitic capacitance between the gate electrode and source/drain regions—all without the cost and difficulties associated with finFET fabrication. FD-SOI is a planar process that provides the benefits of finFET technology without the cost. The first distinguishing feature of FD-SOI is a very thin insulator (buried oxide) placed on top of the substrate, as shown in figure 1. On top of this oxide, a thin silicon film is used to form the transistor channel. In a fully-depleted SOI (as opposed to a partially-depleted SOI), the silicon layer for the transistor channel is thinner, which means that there is no need to dope it during manufacturing, and the channel is fully depleted of mobile charges. There is no floating body effect, and it is easier to control short channel effects [1].
Figure 1. FD-SOI structure.
The primary reason for faster switching times in FD-SOI transistors compared to bulk silicon MOSFETs is the lower capacitance in the device structure. The insulating layer between transistor gate and source/drain reduces parasitic overlap in these electrodes, significantly reducing their effective capacitance. Additionally, the elimination of the thick field oxide found in bulk devices increases switching speeds by reducing charge retention times, because electrons don't have to travel as far when turning off the transistor. This effect is even more pronounced with high-k dielectrics employed in FD-SOI technologies. The FD-SOI architecture also allows designers to change the voltage of the body using the via. Dynamic body biasing via software control enables an active tradeoff of performance vs. power saving [2]. For high-performance or low-voltage applications, the body can be forward-biased, while reverse body bias supports low leakage. While FD-SOI technology was initially used for high-end applications, such as servers and data centers, its low power consumption and high performance, intrinsic compatibility with low-power circuits, and faster switching times compared to bulk silicon MOSFETs, all coupled with the fact that it is easier and cheaper to produce, have made it a widespread choice for mobile applications. However, FD-SOI processes gain even wider applicability when you consider that the channel material is not limited to silicon—innovative combinations of materials, such as FD-SOI channels with embedded high-k gate dielectrics or fully-depleted silicon nanowires (SiNWs), can deliver improved device performance at even lower power consumption.
Verification and simulation of 5G IC designs
Layout verification, which includes PEX, avoids costly foundry re-spins by ensuring the design meets all physical manufacturing requirements (design rules) and performance goals before being sent for production. Foundries require all designs to pass their design rules prior to being submitted for manufacturing to improve the likelihood of a successful yield of chips that perform as intended. Why do engineers also test their ICs in simulations? Because it's hard to predict how an IC will behave once it has been put through its paces by a real-life network! Designers use circuit simulation as a way to test how well the different blocks will work together to achieve the desired performance before actually manufacturing the IC. Doing a re-spin of a chip is very costly at advanced nodes, both in time and resources. Circuit simulations are essential to determine whether a chip will perform correctly and efficiently in whatever type of connection it is used. By testing IC performance in a simulation before the chip is sent to the foundry for manufacturing, designers can understand how well the chip really works, and if more design modifications are needed to meet performance and power targets. Another advantage of computer simulations during the IC design process is that they allow engineers to experiment with different design parameters and layout configurations to find the optimum layout implementation. This layout optimization process also requires accurate PEX to properly model the parasitic resistance, capacitance, and inductance in an IC layout and enable accurate characterization of the chip at high frequencies. Verification and simulation functionality that can address the complex designs and their use of emerging technologies are crucial to the success of the 5G market.
Parasitic extraction
Parasitics (unwanted/unintended resistance, inductance, or capacitance) are an unavoidable occurrence in IC design. Resistance parasitics are due to the opposition of electrons passing through the metal, while capacitance parasitics are caused by the electric field between two conductors. As for inductance parasitics, they are the result of the magnetic field created by passing current through a conductor. While shrinking device sizes and finer line widths allow IC designers to pack more functionality onto a chip, the tighter spacing also generates more parasitics that must be understood and managed. As dimensions get smaller, interactions not only increase between transistors, but also between transistors and interconnects. These interactions become key factors affecting signal delay and other circuit performance metrics. PEX is a two-step process: the first step is intentional device extraction, where designed circuit elements (e.g., transistors, diodes, etc.) are characterized, while the second step is parasitic extraction, in which the unintended electrical characteristics of the routings (resistance, capacitance, and inductance) that connects these circuit elements together are identified and accounted for. 5G parasitic extraction In 5G design, PEX helps engineers validate that the chip designs are able to handle the high demand of a 5G network by enabling them to accurately account for the impact of parasitics on the designed circuit performance. For instance, one integral component of many analog/RF design applications, including 5G technology, is the capacitor— specifically, metal-insulator-metal (MIM) and metal-oxide-metal (MOM) capacitors. With MIM/MOM capacitors, engineers can implement symmetric plate design with high-capacity density (due to minimum width and spacing for metals) that doesn’t compromise the frequency characterization, enabling the layout to achieve the circuit quality set in the design specifications. MIM/MOM capacitors also deliver good matching characteristics, due to lateral coupling. However, the extensive use of MIM/MOM capacitors in 5G designs can present a number of PEX challenges, caused by sensitivity to process variations that affect capacitive accuracy, such as metal and dielectric layer thickness, metal widths, and other variations of process parameters over the wafer. Radio frequency (RF) designers require very accurate device extraction, including the extraction of parasitics inside of the device region, as well as any parasitic interaction of the device geometries with the in-context routing. Flat (rule-based) extraction of designs is typically used down to the device level, including device geometries, because it provides accuracy with faster performance and higher capacity than a full field solver. In 5G applications, however, even close approximations can have a significant negative impact on accuracy. For instance, MOM capacitors have a significant amount of fringe and coupling capacitance between the metal comb structures. In addition, the coupling capacitances from designed capacitors (MOM/MIM) to the surrounding signal nets must be reduced as much as possible and must match very closely. The Calibre® xACT™ platform, which provides fully-integrated rule-based and field solver parasitic extraction, automatically employs the applicable extraction technology to extract all parasitic capacitance components in an analog/RF design and generate a distributed RC netlist of the design that can be used in a downstream post-layout simulation flow. For example, designers must ensure accurate capacitor matching for block-level extraction. Devices such as MOM capacitors can be instantiated as pre-characterized cells (pcells) in the layout. The Calibre xACT platform can speed up extraction at the block level for these types of configurations, because only the interactions between the routing and the pcells are modeled. For nets that exit a pcell through a pin, the coupling capacitance between neighboring nets and nets inside the pcell are extracted, although intentional devices are also netlisted. Another challenge presented by 5G technology is the higher frequencies used in these designs. In direct current (DC) and low frequencies, interconnect impedance is dominated by resistance parasitics. However, as the frequency increases, inductive impedance becomes more dominant and affects signal propagation, introducing skin effect, a phenomenon in interconnect parasitics caused by high frequency. As frequency increases, the current distribution is no longer homogenous across the conductor cross-section. The current tends to flow closer to the conductor surface, increasing the parasitic resistance of the conductor. Skin effects lead to a frequency-dependent value for the effective inductance and resistance seen by the current, which must be included in the extraction to achieve accurate results. Running inductance extraction to account for these impacts during chip design and analysis is extremely important, especially for analog and RF designs that operate at a high frequency, as inductance parasitics can result in reduced gain and bandwidth. The Calibre xL tool provides two principal methodologies for inductance extraction (loop inductance and partial element equivalent circuit, or PEEC) that are accurate and efficient. By including inductance PEX in the design and verification flow, design companies ensure their ICs will deliver the highest possible level of circuit performance and reliability. Calibre xACT, xACT 3D, xRC, and xL tools all use time constant equilibration reduction (TICER), a model order reduction solution, to reduce parasitic netlist size without affecting the accuracy of the netlist, and to speed up downstream simulation and analysis. The Calibre xACT platform functionality provides designers with a fast, highly accurate, and multi-purpose PEX tool with virtually unlimited design scope and fast, scalable performance convenient for analog/RF design characterization, enabling accurate post-layout simulation across a wide range of designs and advanced process nodes.
FD-SOI parasitic extraction
The Calibre xACT platform also provides accurate extraction of parasitics from FD-SOI devices, including connections to neighboring interconnect. Support for FD-SOI processes includes support for multiple base layers, as well as for multiple in-die variation tables, including nested bias tables to account for reactive ion etching (RIE) and optical proximity correction (OPC) process variations during manufacturing. Because there are multiple base layers, with the substrate at different heights, the idea of a parasitic capacitor to “ground” gets more complicated, because where is the ground? Is it the higher ground, or the lower ground? The capacitance value changes depending on this choice, with a higher capacitance value if the ground is closer to the metal interconnect. Multiple base layers The intrinsic capacitance reported from the same metal layer to the different substrates in the FD-SOI construction have different values, because the distance to each substrate is different. These values are captured in the definition in the interconnect process technology (MIPT) file that foundries use as input to the xCalibrate rule file generator to generate parasitic extraction rule files for Calibre xRC and xACT processes. For example, as shown below, designers may define multiple substrate layers with a BFMOAT (boron fluoride moat) in the profile stack using different Z coordinates (height compared to the bottom of the chip). These Z coordinates enable the extraction engine to identify the location of each layer in a stack relative to the Z axis. base = lower_substrate zbottom = -1 thickness = 1 dielectric = bf_moat thickness = 0.2 diel_type = planar eps = 12base = upper_substrate zbottom = 0.2 thickness = 0.01 After defining the base layers with different Z coordinates, the extraction rule files are automatically generated by the xCalibrate process. The Calibre xACT and Calibre xACT 3D tools use those rule files to generate capacitance to the appropriate base layer. Ground layers The Calibre xACT platform uses two methods for extracting ground layers. The proper extraction of ground layers is important for all types of extraction, but is especially important for FD-SOI processes because of the presence of multiple ground layers. The first and most basic method is to define the net name of each ground layer (e.g., VSS) in the PEX NETLIST statement. The PEX NETLIST statement is usually provided in the template file by the foundry, and modified by the design team to meet their needs. The design engineer manually adds the ground name, depending on the name of the ground in the simulation. The second approach is to let the Calibre xACT platform identify the different ground layers (VSS, VSS_A, VSS_D) based on LVS connectivity. Using an LVS check, the Calibre xACT platform determines whether the correct wells are tied to the correct net names. It then uses these correct LVS names to name the wells individually. For example, as shown in figure 2, netA runs over two different ground layers—VSS_A (for analog) and VSS_D (for digital). Each of the coupling capacitors is tied to the correct well, which is essential for extraction accuracy. If there is no well, the layer is given the default name defined in the PEX NETLIST statement (e.g., VSS).
Figure 2. Ensuring the correct wells are tied to the correct net names is especially important for FD-SOI processes because of the presence of multiple ground layers.
The output netlist for this layout: CC1 netA:1 VSS_A 2.2 CC2 netA:2 VSS 3.3 CC3 netA:3 VSS_D 4.4 By defining and extracting each ground layer, designers can split their simulations into three different grounds, and see the individual effects on each ground. For example, the digital ground VSS_D may have a lot of noise injected into it, but the analog ground VSS-A may be quieter. By having the grounds separated, it is possible to model each layer separately. Embedded wells The Calibre xACT platform also supports extraction of embedded wells. Figure 3 shows three embedded wells. The wells are cut out of each other (forming rings), and the over-the-cell routing is grounded to the correct well.
Figure 3. Embedded wells.
This separation of embedded wells is specified in the PEX GROUND LAYER statement, which is typically set up by the foundry: WellA WellB WellC meaning A = A B = B - A C = C - B – A and indicating that WellB will be a ring with the WellA section cut out, and that WellC will be a ring without the WellA or WellB sections.
Conclusion
5G networks offer new opportunities for businesses and individuals to connect in ways we couldn’t even envision a decade ago, but with this opportunity comes a need for chips that can handle the high demand of these networks, and the engineers who can design those chips. Understanding the capabilities of 5G, as well as the design and verification challenges it presents, will enable design companies to implement the necessary processes and tools required to accurately characterize these chips for first tape-out success. With attofarad accuracy, high performance, and advanced device modeling, the Calibre xACT platform provides designers with the flexibility to apply different extraction processes as needed, with Calibre confidence that the results will help ensure their 5G chips meet or exceed yield, performance, and reliability expectations.
恩萊特科技股份有限公司
Enlight Technology Co., Ltd.
www.enlight-tec.com
電話：03-602-7403
傳真：03-621-0304
sales@enlight-tec.com
Comentários