Upcoming Events
- 15TueJunExpanding Opportunity for Industry 4.0 Consultants/WebinarJun 15, 10:00 AMWebinarWith the rapid evolution of customer expectations and innovative technologies, consultants have a unique opportunity to gain a greater share of their existing client base as well as acquire new ones. Today, more than ever, manufacturers are seeking guidance in their quest to becoming more data-drive
- 23WedJunIC設計關鍵－EDA工具介紹與實際案例分享/經濟部工業局南部晶片物聯網智造整合服務基地Jun 23, 2:00 PM – 5:00 PM經濟部工業局南部晶片物聯網智造整合服務基地, No. 6號, Fuxing 4th Road, Qianzhen District, Kaohsiung City, Taiwan 806您知道EDA如何實現IC到電路板、系統的全面性設計解決方案，為不同類型的晶片或感測器加分嗎？ 這堂課將帶您了解EDA為特定晶片或AIoT產品帶來的成果與實際產值，做為工具引進的重要參考！
- 24ThuJunCalibre FullChip & Field Solver solutions for Parasitic Extraction/WebinarJun 24, 11:00 AMWebinarThe Calibre xACT platform, with integrated Calibre xACT 3D and Calibre xL functionality, provides designers with a fast, highly accurate, and multi-purpose parasitic extraction tool that enables post-layout simulation across a wide range of designs and advanced process nodes. With attofarad accuracy
- 29TueJun後疫時代，轉型智慧製造升級新未來/WebinarJun 29, 2:00 PM – 3:15 PMWebinar
- 07WedJul高效平台&曲線Layout除錯技術 加速第三代半導體功率元件的設計與進階驗證/WebinarJul 07, 2:00 PM – 3:00 PMWebinar隨著晶片設計、生產製造技術的成熟與提高，第三代半導體功率元件GaN/SiC、微機電系統MEMS器件、矽光子晶片也延用半導體的生產製造技術，延生出了更多領域的應用，並悄悄改變著我們的生活。這些設計領域與傳統電晶片的版圖設計有什麼不一樣？這些差異在Layout驗證上又會有什麼樣的困難與挑戰？本研討會將介紹如何使用Tanner L-Edit快速完成Layout 及使用Calibre驗證 Design Rule Check (DRC)。
- 08ThuJulPIC circuit optimization using compact models with physical parameters/WebinarJul 08, 10:00 AM ADTWebinarIn this webinar, photonic integrated circuit design, simulation, and optimization will be demonstrated using 3rd party EDA tools combined with Optiwave software. Building fab-based photonic design kit components using 3D EM simulation tools will be shown. Simulation results for a PIC chip optimized
- 14WedJul最易上手的全流程混合信號 IC 設計 EDA 平台/WebinarJul 14, 2:00 PM – 4:00 PMWebinar本次線上研討會將向您介紹並探討如何藉由此簡便且完整的平台，有效提升 Layout 效率及設計生產的良率，透過實際的操作具體呈現如何透過正確使用 EDA 工具讓您的設計開發工作事半功倍！
- TBDTANNER L-EDIT IC/MEMS/LED/Power/Packaging Layout電路佈局及DRC驗證研習 - 新竹場/Location is TBD時間待決定Location is TBDTanner為目前業界做最容易入手且完整的混合信號IC設計全流程平台，目前已經通過全球數千IC設計師實際設計專案及生產驗證。 透過本課程快速了解如何透過Tanner的高效率Layout工具與物理設計規則驗證Design Rule Check. 讓您在MEMS/LED/Power 及Packaging等Layout Driven的GDS設計及進階複雜驗證上更事半功倍。
- TBDTANNER CALIBRE ONE DRC/LVS/XRC 實戰課程 (收費課程)/Location is TBDTime is TBDLocation is TBDConfidently tape out analog/mixed-signal designs with Calibre’s industry-leading DRC, LVS, and parasitic extraction tools.