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中原大學成立「積體電路共構實驗室」 攜手產業培育IC設計人才
中原大學電機資訊學院積體電路共構實驗室揭牌啟用典禮,中原大學董事長張光正致詞。 中原大學電機資訊學院於113年12月19日舉行「積體電路共構實驗室」揭牌啟用典禮,象徵中原大學在培育IC設計專業人才與深化產學合作上的嶄新里程碑。此實驗室不僅展現了中原在半導體與IC設計領域的優...
Dec 27, 20243 min read


恩萊特助光電創新 參展OPTIC 2024
攜手Siemens EDA,以業界標準Calibre DRC為基礎,展示完整矽光子設計與驗證解方 光電學會許晉瑋副秘書長(中)、Siemens EDA 鍾順桐業務協理(右)與恩萊特蘇正宇總經理(左)於現場就光電產業發展與產學合作進行交流。圖/恩萊特科技提供...
Dec 24, 20242 min read


Navigating the complex world of resistance extraction for curvilinear shapes in IC designs
By Nada Tarek As integrated circuit (IC) designs continue to push the boundaries of what’s possible, we’re seeing an explosion in...
Oct 15, 20243 min read


How to get accurate inductance extraction for superconductor ICs
By Hossam Sarhan and Dusan Petranovic Supporting the high performance and reliability needed for artificial intelligence (AI), data...
Oct 8, 20243 min read


The secret to Calibre software quality – AnaCov, our in-house code coverage analysis tool
By Mustafa Naeem, Ahmed Tahoon, Omar Ragi, and Reem El-Adawi In the realm of software testing, accurately tracking and analyzing source...
Sep 3, 20242 min read


How to get accurate inductance extraction for superconductor ICs
By Hossam Sarhan and Dusan Petranovic Supporting the high performance and reliability needed for artificial intelligence (AI), data...
Aug 27, 20243 min read


Using a shift left strategy to address block/chip design challenges during design-stage verification
By David Abercrombie For IC designers, striking the right balance between tight deadlines and limited resources is a constant challenge....
Aug 20, 20243 min read


Unlocking the future with a digital twin for semiconductor manufacturing
By Srividya Jayaram In semiconductor manufacturing, staying ahead means embracing smarter processes. The rise in demand and the need to...
Aug 13, 20244 min read


How to verify well layer connectivity with soft checks
By Terry Meeks In the landscape of modern IC chip verification, ensuring the connectivity from diffusion layers to well regions is...
Aug 6, 20244 min read
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