By Terry Meeks In the landscape of modern IC chip verification, ensuring the connectivity from diffusion layers to well regions is...

By Richard Yan In the intricate world of system-on-chip (SoC) development, Physical Verification (PV) reports serve as vital checkpoints...

By Wael ElManhawy Circuit verification engineers face ever more challenges as semiconductor technology evolves towards smaller process...

By John Ferguson and Nermeen Hossam Chip designers are very aware of how time-consuming early design rule checking (DRC) can be. Not only that, but traditional DRC runs during initial design phases can flood you with errors that may be irrelevant at this early stage. Sorting through these is a massive drain on time that you don’t always have. So let’s talk about Calibre® nmDRC™ Recon, a tool that makes early design rule exploration faster and more efficient. What is Calibre n

By Jeff Wilson Power isn’t just a small factor in the IC design arena—it’s a cornerstone. Design teams work to hit the trifecta of power, performance, and area (PPA) targets that reflect the intended market and functionalities of their products. The journey from concept to physical implementation is one of precision and innovation, as these teams shape layouts that meet these stringent targets. But, as technology pushes into more advanced process nodes, striking a balance bet

By Terry Meeks In the fast-paced world of semiconductor design, time is a critical asset. One way IC designers save time is to...

By John Ferguson IC design’s evolution continues to push the boundaries of Moore’s law to new heights. One of the most intriguing...

By Dilan Heredia and Karen Chow Designing integrated circuits (ICs) for the 3 nm process node poses challenges never seen before. One of...

By John McMillan Most IC designers adopt advanced process technology nodes to benefit from improved performance, density, and functionality while also reducing delays and power consumption through continuous dimensional scaling. The utilization of new device architectures like fin field-effect transistors (finFET), fully depleted silicon-on-insulator (FDSOI), and gate-all-around GAA transistors extends gate length scaling but also results in increased interactions between nei