By David Abercrombie For IC designers, striking the right balance between tight deadlines and limited resources is a constant challenge. Designers are constantly working to enhance efficiency without compromising on design quality. Traditionally, IC design and verification followed a linear process, but modern IC designs require a more concurrent approach that addresses block/chip layout and circuit issues earlier in the design flow. A new approach that provides signoff-quali

By Srividya Jayaram In semiconductor manufacturing, staying ahead means embracing smarter processes. The rise in demand and the need to maximize profits call for innovative solutions to improve yield ramp for new products. Siemens, a pioneer in digital twin technology in multiple industries including energy, factory automation, and aerospace now extends this solution to the electronics and semiconductor manufacturing industry with the Calibre Fab Insights platform. This platf

By John Ferguson and Nermeen Hossam Chip designers are very aware of how time-consuming early design rule checking (DRC) can be. Not only that, but traditional DRC runs during initial design phases can flood you with errors that may be irrelevant at this early stage. Sorting through these is a massive drain on time that you don’t always have. So let’s talk about Calibre® nmDRC™ Recon, a tool that makes early design rule exploration faster and more efficient. What is Calibre n

By Jeff Wilson Power isn’t just a small factor in the IC design arena—it’s a cornerstone. Design teams work to hit the trifecta of power, performance, and area (PPA) targets that reflect the intended market and functionalities of their products. The journey from concept to physical implementation is one of precision and innovation, as these teams shape layouts that meet these stringent targets. But, as technology pushes into more advanced process nodes, striking a balance bet

By John McMillan Most IC designers adopt advanced process technology nodes to benefit from improved performance, density, and functionality while also reducing delays and power consumption through continuous dimensional scaling. The utilization of new device architectures like fin field-effect transistors (finFET), fully depleted silicon-on-insulator (FDSOI), and gate-all-around GAA transistors extends gate length scaling but also results in increased interactions between nei

By John McMillan Today, EDA companies are developing tools and workflows to support HDAP (High-density advanced packaging) LVS/LVL verification. Though the data for achieving “signoff-level” confidence is a work in progress, EDA companies are providing tools that can adapt to different levels of data availability and enable HDAP designers to execute HDAP LVS/LVL flows that are both productive and beneficial. Why is verification for HDAP designs such a challenge? The reality i

By Design With Calibre By Derong Yan Integrated circuit (IC) chip designers are constantly striving to meet ever-increasing standards of reliability and performance in the fast-paced realm of semiconductor manufacturing. Amidst these challenges, plasma induced damage (PID) in gate oxide, often referred to as the antenna effect, stands as a significant threat to the yield and reliability of MOSFET circuits. While PID actually occurs during IC manufacturing, it can be minimized

By Design With Calibre By Terry Meeks Designing integrated circuits (ICs) is a multifaceted task that requires the integration of various components, including intellectual property (IP). IP are reusable components that are integrated into larger IC designs. IP play a crucial role in IC design, enabling design companies to save time and resources by incorporating pre-designed functionality into their layouts. Although companies do develop their own proprietary IP, most IP is

By Design With Calibre By John Ferguson Design teams have known since, well, pretty much forever that mechanical stresses and temperature changes can affect electrical behavior. These impacts change device mobilities and conductivities in active devices, as well as impacting resistivities and electromigration impacts in passive devices,. In traditional integrated circuit (IC) or system-on-chip (SoC) designs, these impacts are largely safeguarded by the fact that all devices a