By John McMillan Most IC designers adopt advanced process technology nodes to benefit from improved performance, density, and functionality while also reducing delays and power consumption through continuous dimensional scaling. The utilization of new device architectures like fin field-effect transistors (finFET), fully depleted silicon-on-insulator (FDSOI), and gate-all-around GAA transistors extends gate length scaling but also results in increased interactions between nei

By John McMillan Today, EDA companies are developing tools and workflows to support HDAP (High-density advanced packaging) LVS/LVL verification. Though the data for achieving “signoff-level” confidence is a work in progress, EDA companies are providing tools that can adapt to different levels of data availability and enable HDAP designers to execute HDAP LVS/LVL flows that are both productive and beneficial. Why is verification for HDAP designs such a challenge? The reality i

By Design With Calibre By Derong Yan Integrated circuit (IC) chip designers are constantly striving to meet ever-increasing standards of reliability and performance in the fast-paced realm of semiconductor manufacturing. Amidst these challenges, plasma induced damage (PID) in gate oxide, often referred to as the antenna effect, stands as a significant threat to the yield and reliability of MOSFET circuits. While PID actually occurs during IC manufacturing, it can be minimized

By Design With Calibre By Terry Meeks Designing integrated circuits (ICs) is a multifaceted task that requires the integration of various components, including intellectual property (IP). IP are reusable components that are integrated into larger IC designs. IP play a crucial role in IC design, enabling design companies to save time and resources by incorporating pre-designed functionality into their layouts. Although companies do develop their own proprietary IP, most IP is

By Design With Calibre By John Ferguson Design teams have known since, well, pretty much forever that mechanical stresses and temperature changes can affect electrical behavior. These impacts change device mobilities and conductivities in active devices, as well as impacting resistivities and electromigration impacts in passive devices,. In traditional integrated circuit (IC) or system-on-chip (SoC) designs, these impacts are largely safeguarded by the fact that all devices a

By Design With Calibre By Le Hong As semiconductor components continue to shrink, the challenges associated with design-for-manufacturing (DFM) and design-technology co-optimization (DTCO) increase. The complexity of the IC design and manufacturing process demands an extension of traditional DFM and DTCO techniques to overcome the systematic failures tied to complex design-process interactions. The IC design-to-manufacturing flow has well-defined modules such as physical desi

By James Paris Hey there, custom integrated circuit (IC) design engineers! If you’re knee-deep in the world of IC design, you know that dealing with fill flows is like walking a tightrope. On one hand, fill data is essential for ensuring your designs meet manufacturing density requirements. On the other hand, they can be a real headache when it comes to managing them effectively within your design environment. But wait, there’s good news! We’ve got a solution that’s going to

By Slava Zhuchenya In the world of semiconductors, creating and verifying IC designs is no cakewalk. It’s a complex dance that involves a bunch of tools and simulations. Design companies rely on electronic design automation (EDA) tools to put IC designs through their paces before hitting the manufacturing line. These EDA tools are used to check if everything’s in order, from design rules to circuit layouts, ensuring that these intricate chips work as intended. Diving into the

By Roger Kang How do you run transistor-level electromigration and voltage drop (EMIR) analysis—command line or an interactive invocation GUI? Does your layout designer have to wait for circuit designers to provide EMIR results and guidance before fixing any violations, and then iterate over and over until all EMIR violations are fixed? Maybe you’d prefer a new approach? How about one that lets layout designers deliver a high quality layout with no design rule checking (DRC),