By Nada Tarek As integrated circuit (IC) designs continue to push the boundaries of what’s possible, we’re seeing an explosion in complexity. From MEMS to 3D ICs, these advanced designs often incorporate curvilinear shapes—those that don’t conform to the typical straight-line, Manhattan-style geometries we’re used to. But while these shapes bring incredible functionality and performance enhancements, they also introduce new challenges in an area that’s crucial for IC reliabil

By Hossam Sarhan and Dusan Petranovic Supporting the high performance and reliability needed for artificial intelligence (AI), data centers and cloud computing requires powerful and efficient integrated circuits (ICs). More semiconductor companies are considering superconductor ICs for their unique properties that allow ultrafast processing of digital information. These properties include fast superconducting transmission lines and active devices called Josephson junctions, w

By Hossam Sarhan and Dusan Petranovic Supporting the high performance and reliability needed for artificial intelligence (AI), data centers and cloud computing requires powerful and efficient integrated circuits (ICs). More semiconductor companies are considering superconductor ICs for their unique properties that allow ultrafast processing of digital information. These properties include fast superconducting transmission lines and active devices called Josephson junctions, w

By David Abercrombie For IC designers, striking the right balance between tight deadlines and limited resources is a constant challenge. Designers are constantly working to enhance efficiency without compromising on design quality. Traditionally, IC design and verification followed a linear process, but modern IC designs require a more concurrent approach that addresses block/chip layout and circuit issues earlier in the design flow. A new approach that provides signoff-quali

By Srividya Jayaram In semiconductor manufacturing, staying ahead means embracing smarter processes. The rise in demand and the need to maximize profits call for innovative solutions to improve yield ramp for new products. Siemens, a pioneer in digital twin technology in multiple industries including energy, factory automation, and aerospace now extends this solution to the electronics and semiconductor manufacturing industry with the Calibre Fab Insights platform. This platf

By John Ferguson and Nermeen Hossam Chip designers are very aware of how time-consuming early design rule checking (DRC) can be. Not only that, but traditional DRC runs during initial design phases can flood you with errors that may be irrelevant at this early stage. Sorting through these is a massive drain on time that you don’t always have. So let’s talk about Calibre® nmDRC™ Recon, a tool that makes early design rule exploration faster and more efficient. What is Calibre n

By Jeff Wilson Power isn’t just a small factor in the IC design arena—it’s a cornerstone. Design teams work to hit the trifecta of power, performance, and area (PPA) targets that reflect the intended market and functionalities of their products. The journey from concept to physical implementation is one of precision and innovation, as these teams shape layouts that meet these stringent targets. But, as technology pushes into more advanced process nodes, striking a balance bet

根據WSTS統計，24Q1全球半導體市場銷售值達1,377億美元，較上季(23Q4)衰退5.7%，較2023年同期(23Q1)成長15.2%；銷售量達2,184億顆，較上季(23Q4)衰退0.6%，較2023年同期(23Q1)衰退2.2%；ASP為0.631美元，較上季(2...

By John McMillan Most IC designers adopt advanced process technology nodes to benefit from improved performance, density, and functionality while also reducing delays and power consumption through continuous dimensional scaling. The utilization of new device architectures like fin field-effect transistors (finFET), fully depleted silicon-on-insulator (FDSOI), and gate-all-around GAA transistors extends gate length scaling but also results in increased interactions between nei