西門子數位化工業軟體今日宣布與聯電（UMC）合作，為聯電的晶圓對晶圓堆疊（wafer-on-wafer）及晶片對晶圓堆疊（chip-on-wafer）技術提供新的多晶片 3D IC 規劃、組裝驗證，以及寄生參數萃取（PEX）工作流程。 據悉，聯電開發出其全新混合鍵合（hybrid-bonding）3D 電路布局驗證（LVS）和寄生參數獲取工作流程，使用西門子 XPEDITION Substrate Integrator 軟體進行設計規劃與組裝，西門子 Calibre 3DSTACK 軟體進行晶片間的連接檢查，同時還使用 Calibre nmDRC 軟體、Calibre nmLVS 軟體及 Calibre xACT 軟體進行 IC 及晶片間延展實體及電路驗證任務。 而在雙方合作後，聯電也將向全球客戶提供此項新流程。藉由在單一封裝元件中提供晶片或小晶片（chiplet）彼此堆疊的技術，企業可以在相同或更小的晶片面積上實現多個元件的功能。與在 PCB 板上擺置多個晶片的傳統系統配置相比，這種方法不僅更加節省空間，而且能夠提供更出色的系統效能及功能以及更

What is 5G and what are its benefits? The fifth generation of mobile telecommunications technology, or 5G, is the next generation of wireless network technology, promising faster data speeds and more bandwidth than ever before. What does that mean for the average person? Think about cellphones, for one. People don't just use their phones for calling or texting anymore—they surf the web, check in with social media apps, watch movies, listen to music playlists, write blogs, tak

Siemens Digital Industries Software today announced a range of expanded electronic design automation (EDA) early design verification functionalities for its Calibre® platform for integrated circuit (IC) physical verification. Engineered to help IC design teams and companies get to tapeout faster, these new capabilities can help IC designers "shift left" their physical and circuit verification tasks by moving the identification, analysis, and resolution of complex IC and syste

By Michael White When you’re flying, it’s fun to look out the window and see clouds from “the other side.” When you’re running an IC design company, clouds take on a whole new perspective as well. Just like planes made it possible to cross continents and oceans in hours rather than days, EDA in the cloud can make it possible to get to tapeouts faster. But, just as we trust planes to carry us safely to our destinations, we also have to trust that running EDA software in the cl

Overview Starting L-Edit The L-Edit UI How to customize your environment Design Setup Masks and Layers Drawing Editing Cells and Hierarchy

MEMS Pro is a flexible, powerful, easy-to-use CAD tool suite for the design and analysis of micro-electro-mechanical systems (MEMS) and other types of sensors and actuators. It offers an integrated solution for the design process that shortens development time while providing designers reliable analysis for manufacture. Functionalities include mixed MEMS/IC schematic capture and simulation, full custom mask layout capability and verification, 3D model generation and visualiza

Using Tanner design tools, TOREX has developed the smallest converters possible without sacrificing functionality and performance. Nobuhiro Aoki, XCL Product Design Group, Product Development Depart, R&D HQ Introduction Tokyo-based TOREX Semiconductor (TOREX) specializes in the development of analog (CMOS) power integrated circuits (ICs). TOREX’s reputation for excellence is readily recognized as its best-in-class ICs achieve the optimum balance between size and cost. TOREX e

Siemens EDA IC 全流程 Siemens EDA 全流程有一個豐富的環境，高度可配置且非常靈活，為混合信號設計人員提供了許多易用功能。該流程經過優化，適用於創建 22nm 的定制模擬 IC 或 “類比為頂層” 的混合訊號 IC。它包含高度集成的前端和後端工具，從原理圖輸入到混合訊號模擬和波形檢索、查看及 RTL 網表綜合，再到佈局佈線、物理版圖實現以及晶圓廠認證的 Calibre® 平臺物理驗證。透過集成協力廠商工具支援互通性、多用戶和版本控制的Open Access 資料格式管控。該全流程套件有一個庫管理器，其為管理和流覽所有設計庫、單元和視圖提供一個統一的介面，並且提供對 IC Manage、Cliosoft 和 SubVersion (SVN) 版本控制軟體的支援。 工藝設計套件 (PDK) 是模擬和定制設計環境的一個重要組成部分，包括 OA 資料、CDF、回檔、網表程式和參數化單元 (PCell)。Siemens EDA 工藝包可以由協力廠商PDK轉換而來，包括回檔和 PCell 代碼。可擴展的自動化質檢流程可以確保Sieme

By Pradeep Thiagarajan Having done IC development for over two decades, I can appreciate the complexities of foundry processes that influence device modeling and silicon fabrication. Semiconductor physics continues to get pushed to newer limits with each technology progression to a smaller process geometry to achieve better PPA (Power/Performance/Area). Chip developers are packing in more features to enhance the customer experience of the end product with focus on quality and