top of page
Search


Accelerate IP design cycles and reduce costs with Calibre design stage verification
By Terry Meeks In the fast-paced world of semiconductor design, time is a critical asset. One way IC designers save time is to...
Jun 25, 20244 min read


Meeting RF design challenges with PADS Professional Premium
By Jim Martens The demand for electronics with gigahertz wireless technology, as well as IoT consumer devices have both increased...
Jun 18, 20242 min read


Unraveling the 3DIC shift left strategy: Navigating the world of multi-dimensional ICs
By John Ferguson IC design’s evolution continues to push the boundaries of Moore’s law to new heights. One of the most intriguing...
Jun 11, 20245 min read


PCB design best practices: power integrity analysis
By Todd Westerhoff What is power integrity analysis? PCB power integrity analysis is the study of a PCB’s Power Delivery Network (PDN),...
Jun 4, 20245 min read


Mastering parasitic extraction at the 3 nm process node
By Dilan Heredia and Karen Chow Designing integrated circuits (ICs) for the 3 nm process node poses challenges never seen before. One of...
May 29, 20245 min read


TSIA 2024年第一季台灣IC產業營運成果出爐
根據WSTS統計,24Q1全球半導體市場銷售值達1,377億美元,較上季(23Q4)衰退5.7%,較2023年同期(23Q1)成長15.2%;銷售量達2,184億顆,較上季(23Q4)衰退0.6%,較2023年同期(23Q1)衰退2.2%;ASP為0.631美元,較上季(2...
May 20, 20242 min read


Parasitic extraction technologies: Advanced node and 3D-IC design
By John McMillan Most IC designers adopt advanced process technology nodes to benefit from improved performance, density, and...
May 14, 20243 min read


Power Integrity Effects of High Density Interconnect (HDI)
High Density Interconnect (HDI) is being used more often to meet the growing need for more complex designs in smaller form factors....
May 1, 20242 min read


The smart path to chiplets using hierarchical device planning and pin regions
Advancements in IC packaging manufacturing, combined with the exploding costs of designing monolithic ICs on today’s advanced process...
Apr 30, 20241 min read
bottom of page
