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Successfully implementing PCB design constraints
By Stephen V. Chavez Last year, on the Printed Circuit Podcast, I spoke with industry veteran, Scott Decker, about the use of PCB design constraints in PCB design. Decker has insightful knowledge on using design constraints as he has been working in the field of board design for 30 years, beginning his career using the Mentor tool in 1990 and spending the past 11 years working in Xpedition . What is a PCB design constraint? In simple terms, a design constraint is a restricti
Aug 1, 20242 min read


A new physical verification reporting solution smooths the on-time tapeout effort
By Richard Yan In the intricate world of system-on-chip (SoC) development, Physical Verification (PV) reports serve as vital checkpoints...
Jul 30, 20242 min read


The foundations and challenges of electronics design data management
By Stephen V. Chavez Last year on the Printed Circuit Podcast I talked with Andre Mosley , a seasoned professional in the field of electronics design, about the critical aspects of managing electronic libraries and design data. This discussion shed some light on the foundational elements, best practices, and ongoing challenges we face in the industry today. Defining the foundation of electronics and electronic libraries Mosley began by clarifying a common misconception in the
Jul 25, 20243 min read


Balancing performance vs. debuggability in LVS circuit verification
By Wael ElManhawy Circuit verification engineers face ever more challenges as semiconductor technology evolves towards smaller process...
Jul 23, 20243 min read


Fundamentals of library and design data management
By Andre Mosley When it comes to electronic systems design, I’m often asked what a robust library and design data management system should include. A centralized library and design data management system should cover the full spectrum of data utilized in developing individual circuit boards or multi-board systems connected by cables. The types of data can be broken down into four categories: Library models : Components, metadata, documents, and electrical models allowing for
Jul 18, 20244 min read


Speeding up early design rule checking with Calibre nmDRC Recon
By John Ferguson and Nermeen Hossam Chip designers are very aware of how time-consuming early design rule checking (DRC) can be. Not only that, but traditional DRC runs during initial design phases can flood you with errors that may be irrelevant at this early stage. Sorting through these is a massive drain on time that you don’t always have. So let’s talk about Calibre® nmDRC™ Recon, a tool that makes early design rule exploration faster and more efficient. What is Calibre n
Jul 16, 20243 min read


Accelerating RF PCB design in a 5G world
By David Wiens The demand for high-speed and efficient RF (Radio Frequency) PCB design has never been greater. With billions of IoT devices expected to come online in the coming years, the necessity for RF design capabilities supporting ultra-fast 5G speeds is becoming increasingly apparent. The 5G revolution: why extreme speed support is crucial Several factors are driving the demand for extreme 5G speed support in RF PCB design. These include: IoT: the Internet of Things is
Jul 11, 20243 min read


Automated analysis-based layout enhancements reduce power grid voltage drops during place & route: A case study with Google
By Jeff Wilson Power isn’t just a small factor in the IC design arena—it’s a cornerstone. Design teams work to hit the trifecta of power, performance, and area (PPA) targets that reflect the intended market and functionalities of their products. The journey from concept to physical implementation is one of precision and innovation, as these teams shape layouts that meet these stringent targets. But, as technology pushes into more advanced process nodes, striking a balance bet
Jul 9, 20243 min read


Accelerate IP design cycles and reduce costs with Calibre design stage verification
By Terry Meeks In the fast-paced world of semiconductor design, time is a critical asset. One way IC designers save time is to...
Jun 25, 20244 min read
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