By Jim Martens The demand for electronics with gigahertz wireless technology, as well as IoT consumer devices have both increased dramatically. This has resulted in the subsequent increase of RF circuitry on designs, which will only continue as we move into the future. The unique design requirements of RF designs An engineer recently told me that their design only had about 10% RF circuitry on it, but that 10% takes up 90% of their design time to complete! This is because RF

By John Ferguson IC design’s evolution continues to push the boundaries of Moore’s law to new heights. One of the most intriguing...

By Todd Westerhoff What is power integrity analysis? PCB power integrity analysis is the study of a PCB’s Power Delivery Network (PDN),...

By Dilan Heredia and Karen Chow Designing integrated circuits (ICs) for the 3 nm process node poses challenges never seen before. One of...

根據WSTS統計，24Q1全球半導體市場銷售值達1,377億美元，較上季(23Q4)衰退5.7%，較2023年同期(23Q1)成長15.2%；銷售量達2,184億顆，較上季(23Q4)衰退0.6%，較2023年同期(23Q1)衰退2.2%；ASP為0.631美元，較上季(2...

By John McMillan Most IC designers adopt advanced process technology nodes to benefit from improved performance, density, and functionality while also reducing delays and power consumption through continuous dimensional scaling. The utilization of new device architectures like fin field-effect transistors (finFET), fully depleted silicon-on-insulator (FDSOI), and gate-all-around GAA transistors extends gate length scaling but also results in increased interactions between nei

High Density Interconnect (HDI) is being used more often to meet the growing need for more complex designs in smaller form factors. Beyond some of the more obvious electrical effects of using smaller vias, there is also an impact to the power integrity of a board using HDI. This includes different effects of mounted inductances of decoupling capacitors, changes in plane performance due to reduction in perforation from chip pinouts, and the inherent plane-capacitance changes f

Advancements in IC packaging manufacturing, combined with the exploding costs of designing monolithic ICs on today’s advanced process nodes, have given rise to a growing trend of disaggregating large SoCs into smaller dies and chiplets. This increased design complexity requires iterative multi-physics analysis during the floorplanning stage and optimization of the design for PPA and cost goals, significantly raising the barrier for project success. Trying to employ traditiona

By John McMillan Today, EDA companies are developing tools and workflows to support HDAP (High-density advanced packaging) LVS/LVL verification. Though the data for achieving “signoff-level” confidence is a work in progress, EDA companies are providing tools that can adapt to different levels of data availability and enable HDAP designers to execute HDAP LVS/LVL flows that are both productive and beneficial. Why is verification for HDAP designs such a challenge? The reality i