High Density Interconnect (HDI) is being used more often to meet the growing need for more complex designs in smaller form factors. Beyond some of the more obvious electrical effects of using smaller vias, there is also an impact to the power integrity of a board using HDI. This includes different effects of mounted inductances of decoupling capacitors, changes in plane performance due to reduction in perforation from chip pinouts, and the inherent plane-capacitance changes f

Advancements in IC packaging manufacturing, combined with the exploding costs of designing monolithic ICs on today’s advanced process nodes, have given rise to a growing trend of disaggregating large SoCs into smaller dies and chiplets. This increased design complexity requires iterative multi-physics analysis during the floorplanning stage and optimization of the design for PPA and cost goals, significantly raising the barrier for project success. Trying to employ traditiona

By John McMillan Today, EDA companies are developing tools and workflows to support HDAP (High-density advanced packaging) LVS/LVL verification. Though the data for achieving “signoff-level” confidence is a work in progress, EDA companies are providing tools that can adapt to different levels of data availability and enable HDAP designers to execute HDAP LVS/LVL flows that are both productive and beneficial. Why is verification for HDAP designs such a challenge? The reality i

By Design With Calibre By Derong Yan Integrated circuit (IC) chip designers are constantly striving to meet ever-increasing standards of reliability and performance in the fast-paced realm of semiconductor manufacturing. Amidst these challenges, plasma induced damage (PID) in gate oxide, often referred to as the antenna effect, stands as a significant threat to the yield and reliability of MOSFET circuits. While PID actually occurs during IC manufacturing, it can be minimized

By Design With Calibre By Terry Meeks Designing integrated circuits (ICs) is a multifaceted task that requires the integration of various components, including intellectual property (IP). IP are reusable components that are integrated into larger IC designs. IP play a crucial role in IC design, enabling design companies to save time and resources by incorporating pre-designed functionality into their layouts. Although companies do develop their own proprietary IP, most IP is

By Design With Calibre By John Ferguson Design teams have known since, well, pretty much forever that mechanical stresses and temperature changes can affect electrical behavior. These impacts change device mobilities and conductivities in active devices, as well as impacting resistivities and electromigration impacts in passive devices,. In traditional integrated circuit (IC) or system-on-chip (SoC) designs, these impacts are largely safeguarded by the fact that all devices a

根據WSTS統計，23Q4全球半導體市場銷售值達1,460億美元，較上季(23Q3)成長8.4%，較2022年同期(22Q4)成長11.6%；銷售量達2,234億顆，較上季(23Q3)衰退5.8%，較2022年同期(22Q4)衰退11.5%；ASP為0.653美元，較上季(...

By Design With Calibre By Le Hong As semiconductor components continue to shrink, the challenges associated with design-for-manufacturing (DFM) and design-technology co-optimization (DTCO) increase. The complexity of the IC design and manufacturing process demands an extension of traditional DFM and DTCO techniques to overcome the systematic failures tied to complex design-process interactions. The IC design-to-manufacturing flow has well-defined modules such as physical desi

By: Deb Geiger, VP Global Marketing, Aegis Software In a manufacturing landscape defined by rigorous standards, emerging technologies,...