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Improving Time-to-Market and Silicon Quality with a Streamlined IP QA Flow
By Wei-Lii Tan Recently Felipe Schneider (from the Solido Crosscheck applications engineering team) and I hosted a live webinar on how to improve time-to-market and silicon quality by utilizing a better IP QA flow. The webinar garnered quite a bit of interest, and we got several great questions from people who tuned in, so I thought I would follow-up here with some additional information. It’s no secret that readily-available, high quality design IP has not only shortened ove
Nov 15, 20212 min read


Get rid of GUI frustration and speed up your Calibre verification job submissions!
By Slava Zhuchenya Graphical user interface (GUI) frustration is real. Deployment of integrated circuit (IC) physical and circuit verification decks to design flows can be tough. First gathering all the correct files, then finding and setting all the correct options and selecting proper checks, can not only be tedious and time-consuming, but also consume valuable resources during the design process. Don’t you think your resources (human AND computing) are better used to ensur
Sep 16, 20212 min read


Can we just agree that perception is everything? Especially in IC design?
By Dennis Joseph Is the dress black and blue, or white and gold? Is that a rabbit or a duck? People looking at the exact same image often see it differently. While it can be fun to argue with friends about trivial disagreements like this one, it’s a lot less fun when you’re designing a computer chip and you’re arguing with your coworkers about how the layout looks. It’s frustrating, and impedes real work getting done. (Okay, maybe arguing with people on Twitter is also frustr
Aug 19, 20213 min read


Efficient package delivery is not just for FedEx!
By John Ferguson Cost, risk, and the limitations of monolithic scaling are driving growth in multi-die (heterogeneous) advanced IC packaging solutions (Whew! That’s a mouthful!). You might also know it by its other name, high-density advanced packaging (HDAP). At Siemens, we’ve spent a fair amount of time researching, working on, and talking about the challenges and opportunities in HDAP design. One thing we’ve learned is that successful HDAP design requires design teams to w
Jul 15, 20211 min read


資訊白皮書 - Tanner: IoT晶片智能化催生新世代IC設計師
本白皮書將簡單介紹了如何使用Tanner設計IC、整合嵌入式軟體、系統探索與記錄及 PCB 設計的設計流程來建立物聯網邊緣裝置。
Feb 8, 20211 min read


資訊白皮書 - 低成本的 TANNER 設計工具、光罩及生產能力大幅降低 ASIC 專案的門檻
本文討論了如何利用多專案晶圓服務以及用於開發混合訊號 ASIC 的低成本設計工具(如 Tanner L-Edit IC)來削減成本與風險。
Jan 22, 20211 min read


【資訊白皮書】利用獨特的 Tanner L-Edit Layout 編輯和驗證功能,因應 MEMS 的設計挑戰 — 第 1 部分
本篇說明了對不規則形狀(包括曲線和全角度多邊形)實作的支援及其易用性,為何是以及如何是使 MEMS 導向的 CAD 工具區別於傳統 IC 導向的工具的重要條件。
Sep 30, 20201 min read


Tanner L-Edit 在封裝佈局GDS (Packaging layout GDS)的應用研習會-熱烈展開
感謝各位朋友撥空參加! 活動熱烈進行中! 恩萊特科技 Enlight Technology Co., Ltd. Mentor, A Siemens Business Authorized Distributor 30286 新竹縣竹北市十興路二段82號2樓 電話:03-602-7403 傳真:03-536-1678 sales@enlight-tec.com
Feb 21, 20201 min read


TANNER L-EDIT IC/MEMS/LED/Power/Packaging Layout電路佈局及DRC驗證研習 - 新竹場 圓滿落幕!
感謝各位業界先進撥冗參加,針對各領域不同應用,在現場有深入熱絡的討論,我們期待下次的研習會,針對不足之處,也很感謝各位指教,謝謝大家的參與! 恩萊特科技 Enlight Technology Co., Ltd. Mentor, A Siemens Business Authorized Distributor 更多研習資訊: www.enlight-tec.com 30286 新竹縣竹北市十興路二段82號2樓 電話:03-602-7403 傳真:03-536-1678 sales@enlight-tec.com
Nov 22, 20191 min read
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