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The three witches: preventing glitch nightmares on CDC paths
As electronic design companies are investing more in automotive and safety-critical designs, there is a renewed focus on design...
Jan 4, 20222 min read


Moore and More 後摩爾時代 - 半導體關鍵技術研討會 精彩活動花絮
恩萊特科技於2021年12月7日舉辦「Moore and More 後摩爾時代 - 半導體關鍵技術研討會」,由學界、業界專家分享目前最新的半導體趨勢與發展,從異質整合、微機電感測器、EDA、HPC,到化合物半導體,邀您共同重溫恩萊特年會精彩每一幕。...
Dec 28, 20211 min read


PADS 應用系列|PADS Standard Plus DFM分析
概述 將DFM分析集成到您的PADS®流程,您可最大限度地減少生產問題,減少每個設計的改版次數,從而縮短產品的上市週期。 PCB製造商的業務目標與您不同,因此您應該先確保設計符合要求且生產就緒,再發送給製造商,這至關重要。例如,製造商更關注利潤,而不太重視設計的長期品質,所以他們可能為加快生產而更改設計,而沒有將更改後的設計回饋給您。 為了保持對設計的控制,你應該在佈局期間找到並解決以下等問題:阻焊細絲、阻焊層暴露的意外覆銅、測試點間距等。投產之前對您的PCB佈局進行製造和裝配驗證,可為您節省資金,並助您更快地將產品推向市場。 PADS DFMA可選功能(僅在PADS Standard Plus提供)包含100多種最常用的製造和裝配分析,可輕鬆識別會導致生產延遲的問題。關鍵網路完成佈線後,您還可以使用PADS分析電路的完整性和時序,並確保電路板投產前滿足所有設計標準。 優勢 投入生產前發現設計中的製造問題 將召回次數降至最低以減少生產延遲 包含100多項最關鍵的製造和裝配相關分析 易用使用者介面 為什麼使用DFM分析? DFM分析可以驗證設計的可
Dec 22, 20212 min read


Moore and More 後摩爾時代 - 半導體關鍵技術研討會 圓滿落幕
由恩萊特科技主辦,國研院半導體中心、國立清華大學智慧環境晶片系統與應用聯盟及國立清華大學微感測器與致動器產學聯盟協辦之「Moore and More 後摩爾時代 - 半導體關鍵技術研討會」於12月7日圓滿落幕。本次研討會由恩萊特科技蘇正宇總經理致歡迎詞並介紹貴賓,緊接著由國...
Dec 8, 20211 min read


Fix first, finish faster!
By James Paris A few years ago, I came across some plans to build a simple bookshelf that would fit perfectly in my home. I already had...
Dec 6, 20212 min read


Enhancing Resiliency in Manufacturing through Connected Platforms, Increased Visibility, and Process
By: Deb Geiger, VP Global Marketing, Aegis Software Enhancing Resiliency in Manufacturing through Connected Platforms, Increased...
Nov 29, 20214 min read


In the EDA world, efficiency + ease of use = productivity (and profitability!)
By Shelly Stalnaker Electronic design automation (EDA) grew out of the need to make it easier and faster to design and manufacture integrated circuits. Nothing has changed since then, except…everything has changed. Just a couple of decades ago, we were entering “unknown territory”—the sub-nanometer era. Today, foundries and design companies are exploring 1nm process nodes. In all that time, the EDA industry constantly expanded functionality to address new design and manufactu
Nov 22, 20213 min read


Improving Time-to-Market and Silicon Quality with a Streamlined IP QA Flow
By Wei-Lii Tan Recently Felipe Schneider (from the Solido Crosscheck applications engineering team) and I hosted a live webinar on how to improve time-to-market and silicon quality by utilizing a better IP QA flow. The webinar garnered quite a bit of interest, and we got several great questions from people who tuned in, so I thought I would follow-up here with some additional information. It’s no secret that readily-available, high quality design IP has not only shortened ove
Nov 15, 20212 min read


西門子與台積電深化合作 持續認證設計工具
西門子數位化工業軟體近日在台積電(2330) 2021開放創新平台 (Online Open Innovation Platform®,OIP) 生態系統論壇中宣布系列與台積電合作帶來一系列的新產品認證,雙方在雲端支援 IC 設計以及台積電的全系列 3D...
Nov 8, 20213 min read
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