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日月光與西門子協同合作下一代高密度先進封裝設計驗證解決方案
日月光與西門子數字工業軟體公司協同合作新的設計驗證解決方案,協助共同客戶更易於建立和評估多樣複雜的IC封裝技術與高密度連結的設計,且能在執行實體設計之前和設計期間使用更具相容性與穩定性的實體設計驗證環境。 高密度先進封裝解決方案(HDAP)源自于日月光參與西門子半導體封裝聯...
Sep 29, 20212 min read


Making sense of cloud EDA
By Michael White and Omar El-Sewefy How to carry out a sensible analysis of cloud EDA’s potential, so you get the right tools and...
Sep 27, 20218 min read


Amplifying Value: The Significant Benefits of Connecting ERP and MES
By: Deb Geiger, VP Global Marketing, Aegis Software Amplifying Value: The Significant Benefits of Connecting ERP and MES As pressures on...
Sep 24, 20215 min read


Caution! Avoid detours when improving resistance on ESD paths
By Derong Yan As overall transistor dimensions shrink, integrated circuit (IC) chip designs become more sensitive to the damage caused by...
Sep 22, 20212 min read


Get rid of GUI frustration and speed up your Calibre verification job submissions!
By Slava Zhuchenya Graphical user interface (GUI) frustration is real. Deployment of integrated circuit (IC) physical and circuit...
Sep 16, 20212 min read


PADS 應用系列|Copper Pour鋪銅優先級使用方法
在PCB設計中,當有多個Copper Pour重疊時,我們可以定義多個優先順序等級來進行灌銅。 如下圖所示兩部分相互重疊的Copper Pour,可以分別設定它們的優先順序進行灌銅。為區別兩個網路,這裡使用不同顏色予以區別。...
Sep 8, 20211 min read


So you think you know symmetry? Think again…
By Sherif Hany “The Art of Analog Layout” is one of the canonical books addressing concepts behind layout design techniques used in...
Sep 6, 20212 min read


PADS 應用系列|阻抗計算設計方法
隨著信號傳送速度迅猛的提高和高頻電路的廣泛應用,對印刷電路板也提出了更高的要求。印刷電路板提供的電路性能必須能夠使信號在傳輸過程中不發生反射、串擾現象,信號保持完整,降低傳輸損耗,起到匹配阻抗的作用,這樣才能得到完整、可靠、精確、無干擾、噪音的傳輸信號。...
Sep 1, 20211 min read


Augmented Reality Delivers Compelling ROI
By: Michael Ford, Sr. Director Emerging Industry Strategy, Aegis Software Investing in the latest technology, even before it is...
Aug 30, 20215 min read
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