By Pradeep Thiagarajan Having done IC development for over two decades, I can appreciate the complexities of foundry processes that influence device modeling and silicon fabrication. Semiconductor physics continues to get pushed to newer limits with each technology progression to a smaller process geometry to achieve better PPA (Power/Performance/Area). Chip developers are packing in more features to enhance the customer experience of the end product with focus on quality and

Introduction The adoption of high-density advanced packaging (HDAP) continues to grow for all kinds of end-user applications. 2.5D integrated circuit (IC) designs using interposers (silicon or organic) generally target high-end applications such as military, aerospace, and high-demand computing, while 3D fan-out packaging approaches like the TSMC integrated fan-out (InFO) package focus more on mass consumption consumer applications like cell phones (figure 1). In addition, al

Place and route (P&R) engineers at MaxLinear strive to achieve high reliability and manufacturability in their SoC designs, while also...

Siemens has collaborated with United Microelectronics Corporation (UMC) to develop process design kits (PDKs) for the foundry‘s 110-nanometer (nm) and 180-nm BCD technology platforms. Siemens Digital Industries Software today announced it has collaborated with United Microelectronics Corporation (UMC) to develop process design kits (PDKs) for the foundry‘s 110-nanometer (nm) and 180-nm BCD technology platforms. The new PDKs for UMC, which is a leading semiconductor foundry fo

As electronic design companies are investing more in automotive and safety-critical designs, there is a renewed focus on design...

By James Paris A few years ago, I came across some plans to build a simple bookshelf that would fit perfectly in my home. I already had...

By Shelly Stalnaker Electronic design automation (EDA) grew out of the need to make it easier and faster to design and manufacture integrated circuits. Nothing has changed since then, except…everything has changed. Just a couple of decades ago, we were entering “unknown territory”—the sub-nanometer era. Today, foundries and design companies are exploring 1nm process nodes. In all that time, the EDA industry constantly expanded functionality to address new design and manufactu

By Wei-Lii Tan Recently Felipe Schneider (from the Solido Crosscheck applications engineering team) and I hosted a live webinar on how to improve time-to-market and silicon quality by utilizing a better IP QA flow. The webinar garnered quite a bit of interest, and we got several great questions from people who tuned in, so I thought I would follow-up here with some additional information. It’s no secret that readily-available, high quality design IP has not only shortened ove

西門子數位化工業軟體近日在台積電（2330） 2021開放創新平台 (Online Open Innovation Platform®，OIP) 生態系統論壇中宣布系列與台積電合作帶來一系列的新產品認證，雙方在雲端支援 IC 設計以及台積電的全系列 3D...