Place and route (P&R) engineers at MaxLinear strive to achieve high reliability and manufacturability in their SoC designs, while also optimizing their power, performance, and area (PPA) design goals. In their effort to minimize debugging time while still ensuring correct-by-construction accuracy, P&R engineers at MaxLinear saw an opportunity to optimize their digital implementation physical verification process by using Calibre RealTime Digital in-design DRC to enable on-demand Calibre signoff DRC within the P&R environment.
Adopting Calibre RealTime Digital for in-design AMS design rule checking verification speeds design closure
Automated design enhancements during P&R can create layout variances that lead to complex (DRC errors at the chip level, such as top-level/IP blocks interface, or “last mile” functional/timing ECO errors. The intricacy of these types of errors typically require P&R engineers to manually debug and correct during DRC closure. By enabling fast, iterative signoff DRC checking and fixing during floorplanning and placement, the Calibre RealTime Digital interface not only reduces batch DRC iterations, but also eliminates potential late-stage issues during final physical verification signoff that are exponentially harder to fix. Adopting the Calibre RealTime Digital interface enabled MaxLinear designers to accelerate their DRC closure and save weeks in their tapeout schedules for all designs at all nodes.
恩萊特科技股份有限公司
Enlight Technology Co., Ltd.
www.enlight-tec.com
電話：03-602-7403
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sales@enlight-tec.com
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