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In the EDA world, efficiency + ease of use = productivity (and profitability!)
By Shelly Stalnaker Electronic design automation (EDA) grew out of the need to make it easier and faster to design and manufacture integrated circuits. Nothing has changed since then, except…everything has changed. Just a couple of decades ago, we were entering “unknown territory”—the sub-nanometer era. Today, foundries and design companies are exploring 1nm process nodes. In all that time, the EDA industry constantly expanded functionality to address new design and manufactu
Nov 22, 20213 min read


Improving Time-to-Market and Silicon Quality with a Streamlined IP QA Flow
By Wei-Lii Tan Recently Felipe Schneider (from the Solido Crosscheck applications engineering team) and I hosted a live webinar on how to improve time-to-market and silicon quality by utilizing a better IP QA flow. The webinar garnered quite a bit of interest, and we got several great questions from people who tuned in, so I thought I would follow-up here with some additional information. It’s no secret that readily-available, high quality design IP has not only shortened ove
Nov 15, 20212 min read


西門子與台積電深化合作 持續認證設計工具
西門子數位化工業軟體近日在台積電(2330) 2021開放創新平台 (Online Open Innovation Platform®,OIP) 生態系統論壇中宣布系列與台積電合作帶來一系列的新產品認證,雙方在雲端支援 IC 設計以及台積電的全系列 3D...
Nov 8, 20213 min read


We know…power integrity analysis can be a really big pain, especially for really big designs
By Joe Davis Design teams use power integrity analysis to determine if the circuits in their designs will provide the intended...
Nov 4, 20213 min read


Don’t like standing in lines? Get with the (right) programs!
By John Ferguson For a while, it appeared that the worst of the COVID pandemic was behind us. My mind immediately began focusing on a...
Oct 25, 20212 min read


Improving consistency of NLDM and CCS models for better signoff convergence
By Tina Durgia The semiconductor industry has come a long way in terms of the technological advancements and growth. Thanks to these...
Oct 21, 20212 min read


Custom layout designers…Want to know a secret? You can close DRC faster. A lot faster…
By Srinivas Velivala Design rule checking (DRC) closure is a “tax” that custom layout designers must pay at all process nodes. Ask all...
Oct 11, 20213 min read


日月光與西門子協同合作下一代高密度先進封裝設計驗證解決方案
日月光與西門子數字工業軟體公司協同合作新的設計驗證解決方案,協助共同客戶更易於建立和評估多樣複雜的IC封裝技術與高密度連結的設計,且能在執行實體設計之前和設計期間使用更具相容性與穩定性的實體設計驗證環境。 高密度先進封裝解決方案(HDAP)源自于日月光參與西門子半導體封裝聯...
Sep 29, 20212 min read


Making sense of cloud EDA
By Michael White and Omar El-Sewefy How to carry out a sensible analysis of cloud EDA’s potential, so you get the right tools and...
Sep 27, 20218 min read
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