By Hossam Sarhan and Alexandre Arriordaz With the increasing complexity of design layouts and shorter tapeout cycles, waiting until signoff verification to find and correct errors is no longer practical for integrated circuit (IC) design teams. To achieve tapeouts on schedule, designers must now apply reliability verification checks throughout the design flow, from intellectual property (IP) level to full-chip level, to ensure they meet design schedules while confirming desig

By James Paris The OASIS* database format is a widely used industry standard in electronic design automation (EDA) software for integrated circuit (IC) design flows. While the OASIS standard provides a set of rules for the format and content of the file, different EDA tools may create different solutions to represent the same layout in OASIS format. These variations in the content and structure of the resulting databases may cause significant issues in the production IC desig

By Richard Yan Are you interested in optimizing your integrated circuit (IC) physical verification (PV) flows? How does automating the tedious manual setup of your PV jobs sound? With the option to save your configuration for future iterations? All this and more can be achieved with the user-friendly Calibre® Interactive graphic user interface (GUI), saving you time and effort in your iteration cycles, and boosting designer confidence! With the never-ceasing advance through I

西門子數位化工業軟體日前在台積電2023 年北美技術研討會上公布一系列最新認證。多項EDA（電子設計自動化）解決方案獲得台積電包括5奈米以下，包括N3E及N2等最先進製程認證，對台積電最新製程提供全面支援。 西門子的 Analog FastSPICE 平台也成功獲得台積電5奈米的N5A、3奈米N3E和2奈米的N2等先進製程認證，可用於為奈米級類比、無線射頻（RF）、混合式訊號、記憶體和客製化數位電路提供電路驗證。 此外，Analog FastSPICE 平台作為台積電 N3E 和 N4P 製程客製化設計參考流程（CDRF）的一部分，現支援台積電的可靠性感知模擬技術，可解決IC 老化和即時自體發熱效應，並提供其他進階的可靠性功能。 台積電的 N4P CDRF 也包含西門子的 Solido Variation Designer 軟體，可用於 high sigma 的進階變異感知驗證。 西門子還進一步增強其 Tanner軟體，協助客戶進行下一代類比與混合訊號 IC的設計和布局。透過與台積電團隊的密切合作，Tanner 設計平台現能高效完成台積電 16n

The manufacturing industry is constantly evolving, and manufacturers know they must adjust to changes in engineering, customer demands,...

Siemens Digital Industries Software announced today at the TSMC 2023 North America Technology Symposium a range of new certifications and collaborations with longtime partner TSMC, resulting in key achievements toward enabling Siemens EDA technologies for the foundry’s latest process technologies. Calibre platform certified for N3E processes Siemens’ industry-leading Calibre® nmPlatform tool for integrated circuit (IC) verification sign-off is now fully certified for TSMC’s a

By John Ferguson In recognition of the growing need for a more holistic approach to three-dimensional integrated circuit (3DIC) design, TSMC introduced their 3DFabric™ technologies in 2020 to incorporate system design, 3D stacking, and their advanced packaging technologies, such as TSMC-SoIC™, InFO, and CoWoS®. That was quickly followed by the formation of the TSMC Open Innovation Platform® (OIP) 3DFabric Alliance to accelerate 3DIC ecosystem innovation and readiness even fur

By Kesmat Shahin How many times, as you traversed across design stages and ran countless iterations, have you wished that you had a superpower to let you accomplish 100 things at the same time? Oh, and maybe a magic wand, so you could find and fix just actionable errors without even debugging? Unfortunately, superpowers and magic wands are pretty hard to come by in integrated circuit (IC) design, but with Calibre nmLVS Recon early design layout vs. schematic (LVS) checking, S

Horsham, PA (March 30, 2023) — Aegis Software, a global provider of Manufacturing Operations Management Software, announces new...